International Workshop on Logic Synthesis
        Research Triangle Park, North Carolina, USA
                 May 7-10, 1991               
                   Sponsored by MCNC
                    In Cooperation with
            acm SIGDA and IEEE Circuits and Systems Society

                       PROGRAM         
1.1  Redundancy identification and Removal Based on BDDs and implicit State Enumeration.
           H. Cho, G.D. Hachtel. F. Somenzi,. University Of Colorado - Boulder.
1.2  An ATPG-Based Approach to Sequential Logic Optimization. 
           K.-T. Cheng; AT&T Bell Labs.
1.3  Exact Redundant State Registers Removal Based on Binary Decision Diagrams.
           B. Lin, A. R. Newton; UC-Berkeley.
2.1  Specification, Synthesis, and Verification of Hazard-Free Asynchronous Circuits.      I
           C.W. Moon, P.R. Stephan, R.K. Brayton; UC-Berkeley.                  /
2.2  A Local Optimization Technique for Asynchronous Control Circuits. 
          P. Vanbekbergen, G. Goossens. H. De Man; lMEC Laboratory.        .
2.3  Asynchronous State Machine Synthesis Using a Local Clock, 
           S.M. Nowick, D.L Dill; Stanford University
3.1 Retiming of Circuits with Single Phase Transparent Latches.
    N. Shenoy. R.K. Brayton, A. Sangiovanni-Vincentelli; UC-Berkeley.
3.2 Partitioning Sequential Circuits for Logic Optimization. 
    S. Dey, Duke University; F. Brglez. MCNC; G. Kedem, Duke University
4.1 On Application of Boolean Unification to Combinational Logic Synthesis.
   �@M. Fujita. Y. Matsunaga. T. Kakuda. K.-C. Chen; Fujitsu Labs.
4.2 Heuristic Minimization of Boolean Relations.
    Y. Watanabe. R.K. Brayton; UC-Berkeley.
5.1 Incremental Synthesis for Engineering Changes.
    Y. Watanabe, R.K. Brayton; UC-Berkeley.
5.2 The Timing of Synthesis. 
    D. Brand,. IBM.
6.1a  Derivation of Don't Care Conditions by Perturbation Analysis of Combinational
      Multiple-Level Logic Circus.
      M. Damiani, G. De Micheli; Stan ford University.
6.2a  The Use of Image Computation Techniques in Extracting local Don't Cares and Network Optimization.
     H. Savoj, R.K. Brayton, UC-Berkeley; H.J. Touati, DEC PRL.
6.1b  Don't Care Sequences and the optimization of interacting Finite State Machines.
      J.-K. Rho, G. Hachtel, F. Somenzi'; University of Colorado at Boulder.
6.2b  Restructuring And Resynthesis of Sequential Systems Using interval Don't Cares.
       D. Bostick, M. Lightner; University of Colorado at Boulder.   
6.3b  Preserving Don't Care Conditions during retiming
      E.M. Sentovich, R.K. Brayton; UC-Berkeley.
7.1  Path Sensitization Conditions and Delay Computation in Combinational Logic Circuits.
     S. Devadas, MIT; K. Keutzer. Synopsys; S. Malik. Princeton              .
7.2  Ting Analysis and Delay-Fault Test Generation Using Path Recursive Function
     P.C. McGeer, University of British Columbia; A. Saldanha. P. Stephan, R.K. Brayton. 
     A.L. Sangiovanni-Vincentelli. UC-Berkeley.
8.1  Performance Enhancement through the Generalized Bypass Transform      '
     P.C. McGeer, University of British Columbia; R.K. Brayton. 
     A.L. Sangiovanni-Vincentelli, UC-Berkeley, S. Sahni, University of Florida.
8.2  Delay Optimization of Combinational Logic Circuits through Clustering and Partial Collapsing. 
     H. J. Touati, H. Savoj, R.K. Brayton; UC-Berkeley.
9.1a Verification of Relations between Synchronous Machines.
     F. Van Aelten, J. Allen, S. Devadas; MIT
9.2a Variable Ordering for FSM Traversal.
     S.-W. Jeong. a. Plessier, G.D. Hachtel, F. Somenzi; University of Colorado at Boulder.
9.1b  Combinational and Sequential Logic Verification Using General Binary Decision Diagrams.
     P. Ashar, A. Ghosh. UC-Berkeley; S. Devadas, MTT; A.R. Newton; UC-Berkeley.   .   -
9.2b  A Mixed Depth-First/Breadth-first Traversal Technique for Sequential Logic Verification.
     A. Ghosh. UC-Berkeley; S. Devadas, HIT.

Posters
       Controllability Factoring and its Application to Timing optimization, 
      K. McElvain; Mentor Graphics Corp.

       Implicit Manipulation of Equivalence Classes using binary Decision Diagrams, 
       B. Lin. A.R. Newton;    UC-Berkeley.                                       .

       improved Scripts in MIS-II for Logic Minimization of Combinational Circuits.
       H. Savoj. H-Y. Wang. R. Brayton; UG-Berkeley.
       Performance Directed Technology Mapping Using Constructive Matching.
       C. Liem, M. Lefebvre;  Carleton University.          I
       Performance Improvement through optimal Clocking and retiming. 
       T. M. Burks, K.A. Sakallah.  University of Michigan; K. Bartlett, G. Borriello, University of Washington.
       Synthesis of Complex Controllers Using a ROM Generator. 
       L. Gerbaux. G. Saucier; institute National Polytechnique de Grenoble/CSI.                       .
       Technology Mapping for Table-look-up Programmable Gate Array.
       M. Groh, W. Rosenstiel: University  of Karlsruhe.

10.1 On the Minimization of And-EXOR Expressions.
      D. Brand, lBM; T. Sasao, Kyushu institute of Technology.
10.2  Dual global Flow. 
      L. Berman. R. Damiano; IBM.
10.3  Concurrent Resynthesis for Network Optimization.
      K-C. Chen, Fujitsu America; M. Fujita; Fujitsu Labs 
10.4 MDriver: A Strategy Generator for Multiple-Level optimization.
    M. Pipponzi; SGS-Thomson Microelectronics.
11.1 Layout Considerations in Combinational Logic Synthesis.
     M. Pedram, N. Bhat, K. Chaudhary, S. Mayrhofer. E.S. Kuh; UC-Berkeley.
11.2 Lexicographical Expression of Boolean Functions and Applications to Logic Synthesis ,
   P. Abouzeid, T. Besson, E. Chotin, M. Crastes, J. From, K. Sakouti. G. Saucier, P. Sicard. 
   Istitut National Polytechnique de Grenoble/CSI; F. Poirot. VLSI Technology lnc.     .
11.3  Technology mapping for Delay Optimization of look table-Based FPGAs.
     R. Francis, J. Rose, Z. Vranesic; University of Toronto.