Advance Program and Registration IWLS '93: International Workshop on Logic Synthesis Granlibakken Conference Center, Tahoe City, CA, May 23-26, 1993 ----------------------------------------------------------------------------- Advance Program Sunday, May 23 6-10 PM: Dinner Reception & Poster Hanging (NB: All posters will remain up for the duration of the meeting. Poster presenters guarantee to be present at their poster at the scheduled time, but may be present at other times, as well) Monday, May 24 7:30-8:15 Breakfast 8:15-8:30 Welcome, R. Rudell, Technical Program Chair 8:30-9:30 Asynchronous Design (G. Saucier) 1a: Concurrency Reduction Transformations on State Graphs for Asynchro- nous Circuit Synthesis C. Ykman-Couvreur, P. Vanbekbergen, B. Lin, IMEC. 1b: Generalizing Signal Transition Graphs for Modeling Mixed Asynchro- nous/Synchronous and Arbitration Behavior. P. Vanbekbergen, C. Ykman-Couvreur, B. Lin, H. de Man, IMEC 1c: Unifying Synchronous/Asynchronous State Machine Synthesis K. Yun, D. Dill, Stanford University 9:30-10:00 Poster Session 1 P1a: A Criterion for Logic Gate Models P. Stephan, R. Brayton, UC Berkeley P1b: Synthesis Control Mechanism for a Multi-module Design and Hazard- ous Flow-through Detection O. Ilan, Zoran Microelectronics P1c: Self-Timed Finite State Machine: From Example to Synthesis V. Varshavsky, V. Marakhovsky, University of Aizu Aza Kami-Iawase 90 P1d: The Decomposition and Synthesis of FSM W-L Yang, R. Owens, M. J. Irwin, Penn State University 10:00-10:30 Break 10:30-11:30 New Results in Switching Theory (A. Saldanha) 2a: Some Results on the Complexity of Boolean Functions for Table LookUp Architectures R. Murgai, R. Brayton, A. Sangiovanni-Vincentelli, UC-Berkeley 2b: A Fully Implicit Quine-McCluskey Procedure Using BDD's G. Swamy, R. Brayton, P. McGeer, UC-Berkeley 2c: Analysis of Cyclic Combinational Circuits S. Malik, Princeton University 11:30-12:00 Poster Session 2 P2a: Disjoint Decomposition with Partial Vertex Chart S. He, M. Torkelson, Lund University P2b: A Breakthrough in Two-Level Logic Minimization O. Coudert, H. Fraisse, J-C. Madre, Bull P2c: An Algorithm for Verifying the Equality of Signature Cubes P. McGeer, J. Sanghavi, R. Brayton, A. Sangiovanni-Vincentelli, UC- Berkeley P2d: Improving Finite State Assignment for Two-Level Programmable Logic Devices S. Hassoun, G. Borriello, University of Washington 12:00-1:30 Lunch 1:30-2:30 BDD Applications (E. Clarke) 3a: Dynamic Variable Ordering for Ordered Binary Decision Diagrams R. Rudell, Synopsys 3b: Efficient Boolean Matching Based on Unique Variable Ordering U. Schlichtmann, TU-Munich, F. Brglez, MCNC, P. Schneider, TU- Munich 3c: Boolean Matching Based on Boolean Unification K-C Chen, Fujitsu America 2:30-3:00 Poster Session 3 P3a: Minimal Multi-Level Realization of Switching Functions Based on Kro- necker Functional Decision Diagrams A. Sarabi, P. Ho, K. Iravani, R. Daasch, M. Perkowski, Portland State U. P3b: Use of Binary Decision Diagrams for Logic Synthesis G. Saucier, B. Babba, H. Bouzouzou, INPG, F. Poirot, R. Roane, Com- pass Design Automation P3c: Equality Checking of Two Logic Circuits with Different Internal Variables Using BDD's S. Kimura, Kobe University P3d: Iterating Variable Ordering Heuristics to Compute Small Ordered Binary Decision Diagrams S. Soe, K. Karplus, UC-Santa Cruz 3:00-3:30 Break 3:30-4:30 Wave Pipelining and Pattern Recognition (K. McElvain) 4a: Minimum Padding to Satisfy Short Path Constraints N. Shenoy, R. Brayton, A. Sangiovanni-Vincentelli, UC-Berkeley 4b: Logic Restructuring for Wave-pipelined Circuits T.-S. Kim, W. Burleson, M. Ciesielski, University of Massachusetts 4c: Logic Minimization as a Robust Pattern Finder T. Ross, M. Noviskey, Wright Laboratory, M. Axtell, Veda, Inc. 4:30-5:30 Poster Session 4 P4a: TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry M. C. Papaefthymiou, K. Randall, MIT P4b: Combinational and Sequential Timing Optimization Techniques by Local Transformation S. Yang, Pusan National University P4c: Heuristics for Shannon Decompostion in Area-Efficient Realization of Fully Robust Path Delay Fault Testable Digital Logic B. Kapoor, Texas Instruments, V. Nair, Southern Methodist Univ. P4d: A Study of Theoretical Issues in the Synthesis of Delay Fault Testable Circuits S. Chakravarty, SUNY-Buffalo 6:00-8:00 Dinner, Granlibakken 8:00-10:00 Panel Tuesday, May 25 7:30-8:30 Breakfast 8:30-9:30 Finite State Machine Specification (G. Borriello) 5a: Synthesis of Controllers from Interval Temporal Logic Specification M. Fujita, Fujitsu, S. Kono, Sony 5b: Optimized Controller Synthesis Using Esterel G. Berry, INRIA, H. Touati, DEC-PRL 5c: A Synthesis Framework Based on Trace and Automata Theory J. Fron, J. Yang, M. Damiani, G. De Micheli, Stanford University 9:30-10:00 Poster Session 5 P5a: A Framework for Multi-Level Synthesis from VHDL S. R. Shah, J. G. Tront, Virginia Polytechnic Institute P5b: Design as an Extension: A New Design Direction D. Benson, V. Malbasa, Washington State University P5c: An Efficient State Minimization Algorithm for Finite State Machines R. Puri, J. Gu, University of Calgary P5d: FSM State Assignment for Improved Testability T. Muller, F. Pichler, Johannes Kepler University 10:00-10:30 Break 10:30-11:30 New BDD Applications (M. Fujita) 6a: Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation E. Clarke, M. Fujita, Fujitsu, P. McGeer, UC-Berkeley,K. McMillan, CMU. J. Yang, Stanford University, X. Zhao, CMU 6b: A Symbolic Algorithm for Maximum Flow in 0-1 Networks G. Hachtel, F. Somenzi, University of Colorado 6c: Ternary Decision Diagrams and their Application T. Sasao, Kyushu Institute of Technology 11:30-12:00 Poster Session 6 P6a: On Computing the Transitive Closure of a State Transition Relation Y. Matsunaga, Fujitsu, P. McGeer, R. Brayton, UC-Berkeley P6b: Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping E. Clarke, CMU, M. Fujita, Fujitsu, P. McGeer, UC-Berkeley, K. McMillan, CMU, J. Yang, Stanford University, X. Zhao, CMU P6c: BDD Representation of Incompletely Specified Functions S. Chang, M. Marek-Sadowska, UC-Santa Barbara P6d: A Communication Complexity Based Approach to BDD Variable Order- ing for Systems of Interacting Finite State Machines A. Aziz, S. Tasiran, R. Brayton, UC-Berkeley 12:00-1:30 Lunch 1:30-2:30 Sequential Don't Cares (G. De Micheli) 7a: Permissible Observability Relations in Interacting Finite State Machines H-Y Wang, R. Brayton, UC-Berkeley 7b: Multiple Boolean Relations E. Sentovich, V. Singhal, R. Brayton, UC-Berkeley 7c: Heuristic Minimization for Synchronous Relations V. Singhal, Y. Watanabe, R. Brayton, UC-Berkeley 2:30-3:00 Poster Session 7 P7a: Computation of Sequential Input Don't Care Sequences in FSM Net- works of Arbitrary Topologies H-Y Wang, R. Brayton, UC-Berkeley P7b: The Application of a Hopfield Neural Network for Scheduling and Allo- cation in Behavioral Synthesis D. Gassen, J. Carothers, University of Arizona P7c: Tuning of Logic Synthesis Scenarios L. van Ginneken, A Kuehlmann, IBM P7d: Evaluation of Logic Synthesis Tools for Field-Programmable Gate Arrays F. Zhou, Penn State University, O. Rettig, U. Baitinger, Univ. Stuttgart 3:00-3:30 Break 3:30-4:30 Technology-Driven Synthesis (L. Trevillyan) 8a: Dedicated Factorization Techniques for Complex Logic Blocks M. Belrhiti, G. Saucier, INPG, P. Abouzeid, Innovative Synthesis Tech- nologies 8b: Improving Cell Libraries for Synthesis K. Keutzer, K. Scott, Synopsys 8c: Computing the Entire Active Area versus Delay Trade-off Curve for Gate Sizing with a Piecewise Linear Simulator P. Buurman, M. Berkelaar, J. Jess, TU-Eindhoven 4:30-5:00 Poster Session 8 P8a: Experiments with Cell-Based Datapath Synthesis M. Mahmood, A. Ginetti, C. Kingsley, Compass Design Automation P8b: Improving the Routability of Synthesized Designs K. Keutzer, A. Wang, Synopsys P8c: Functional Netlist Partitioning Strategies and Applications to FPGA Synthesis D. Brasen, J. Hiol, G. Saucier, INPG P8d: Synthesis of Multipliexer Directed-Acyclic Graph Network with Applica- tion to FPGA's and BDD's H. Wu, M. Perkowski, N. Zhuang, Portland State University 5:00 Board Bus For South Lake Tahoe 6:00-10:00 Banquet, Tahoe Queen 10:00 First Bus back to Granlibakken 12:00 Second (& last) bus for Granlibakken Wednesday, May 26 7:30-8:30 Breakfast 8:30-9:30 Technology Mapping: F. Mailhot 9a: Low-Power Driven Technology Mapping under Timing Constraints B. Lin, H. de Man, IMEC 9b: FGMap: A Technology Mapping Algorithm for Look-Up Table Type FPGAs based on Function Graph Y-T Lai, K-R Pan, M. Pedram, USC 9c: Inverter Minimization in Logic Networks A. Jain, R. Bryant, CMU 9:30-10:00 Poster Session 9 P9a: A Method of Logic Mapping for Fine Grain FPGA's N. Song, M. Perkowski, Portland State University P9b: Library-based Mapping for LUT FPGAs Revisted N. Bhat, UC-Berkeley P9c: An Experiment in Technology Mapping for FPGA's using a Fixed Library L. Trevillyan, IBM P9d: Placement and Placement Driven Technology Mapping for FPGA Syn- thesis T. Gao, C. Liu, University of Illinois, K-C Chen, Fujitsu America, J. Cong, Y. Ding, UCLA 10:00-10:30 Break 10:30-11:30 Combinational Don't-Cares (S. Malik) 10a: Maximum Projections of Don't Care Conditions in a Boolean Network T. Stanion, C. Sechen, University of Washington 10b: Observability Relations for Multi-Output Nodes H. Savoj, R. Brayton, UC-Berkeley 10c: Identification of Non-testable Multifaults A. Malik, D. Brand, IBM 11:30-12:00 Poster Session 10 P10a: An Approach to Generation of Don't Care Sets after Technology Map- ping A. Zemva, University of Ljubljana, F. Brglez, K. Kozminski, MCNC P10b: An Efficient False Path Elimination Algorithm R. Attarha, TU-Berlin 12:00-2:00 Lunch and Planning Session for IWLS 9x