IWLS-99 Program

Sunday, June 27

6:00-10:00pm: Dinner reception and Poster Hanging

(NB: All posters will remain up for the duration of the meeting. Poster presenters guarantee to be present at their poster at the scheduled time, but may be present at other times)

Monday, June 28

8:30-9:50 Session 1: Buffering and Fanout Optimization

1. On The Global Fanout Optimization Problem
   Rajeev Murgai

2. Buffering Large Networks by Lagrangian Relaxation
   I-Min Liu

3. Fanout Optimization Using a Gain-based Delay Model
   Peyman Rezvani, Amir H Ajami, Massoud Pedram, Hamid Savoj

9:50-10:30 BREAK and Poster Session 1

1. Logic synthesis based on the structure of an ordered DD
   M. A. Thornton

2. Stochastic Cycle Period Analysis in Timed Circuits
   Eric Mercer

3. Clan-Based Structural Circuit Decomposition
   Soha Hassoun

4. Functional Decomposition for FPGA-based designs...
   Henry Selvaraj

5. Functional Decompositions using an Automatic Test Pattern Generator and a Logic Simulator
   Tsutomu Sasao, Seiji Kajihara

6. Parallel Technology Mapping for LUT-based FPGA using Partitioning
   Laurent Lemarchand

7. Covering Strategies for Library Free Technology Mapping
   Andre Reis, Ricardo Reis

8. New Heuristic Algorithms for the logic minimization
   Muhammad Ayyaz

10:30-11:50 Session 2: BDD construction and minimization

1. Complexity of OBDD Construction
   Jawahar Jain

2. Algorithmic Considerations for OBDD Reordering
   Christoph Meinel

3. Solving the Multiple Variable Order Problem for Binary Decision Diagrams by Use of Dynamic Reordering Techniques
   Christoph Scholl

11:50-1:00 Focus Groups I

1:00-2:00 LUNCH

2:00-3:20 Session 3: Asynchronous circuits

1. Towards a language-based design flow for asynchronous circuits
   Ivan Blunno, Luciano Lavagno

2. Direct Synthesis of Timed Asynchronous Circuits
   Sung Tae Jung

3. Relative timing based verification of timed circuits and systems
   Hoshik Kim

3:20-4:00 BREAK and Poster Session 2

1. Synthesis of Hardware from Affine Recurrence Equations
   Jason Crop

2. Lazy Group Sifting for Efficient State Traversal
   Hiroyuki Higuchi, Fabio Somenzi

3. Generating Regular Arrays Using Symmetry Chain
   Wei Wang

4. A formal design environment for Sonet/SDH ASICs
   Werner Haas

5. Usefulness of Recursive and Component Reuse in Synthesising VHDL Designs
   Azeddien Sllame

6. Formal verification of high-level designs in VHDL
   Shahid Ikram

7. A datapath design advisor for high-performance designs
   Vivek Tiwari

8. Programming environment for manipulation of state machines
   Oliver Kraus

9. Synthesis of Dynamic Digital Controllers And the Case for Natural Logic
   Charles Moeller

4:00-5:20 Session 4: Formal Verification

1. Incremental CTL Model Checking
   Jae-Young Jang, In-Ho Moon, Gary D Hachtel

2. Least Fixed Point MBM: Improved Technique for Approximate Reachability
   In-Ho Moon

3. Finding Maximal Symmetric Groups of Variables in Incompletely Specified Boolean Functions
   Chih-Wei Chang

6:00-8:00 Dinner

8:00-10:00 Panel: Logic synthesis - where is the next impact?

Tuesday, June 29

8:30-9:50 Session 5: BDD applications

1. BDD decomposition for efficient logic synthesis
   Congguang Yang

2. Composition of Reduced Ordered Binary Decision Diagrams
   Elena Dubrova

3. Evaluation of OBDD Heuristics via the Internet
   Christoph Meinel

9:50-10:30 BREAK and Poster Session 3

1. Accurate interconnect timing analysis needs a frequency-domain simulation
   F Huret

2. Yet Another Decision Diagrams: theoretical properties of a layout-friendly functional representation
   Luca Macchiarulo, Malgorzata Marek-Sadowska

3. Slack Equalization Algorithm: Precise Slack Distribution for Low-Level Synthesis and Optimization
   Chunhong Chen, Majid Sarrafzadeh

4. Synthesis of Two-level Dynamic CMOS Circuits
   Amar Mukherjee, Ajit Pal

5. Post-layout management of delay-power constraints
   Nadine Azemard

6. Synthesis for mixed CMOS/PTL logic: preliminary results
   Congguang Yang

7. Accurate power estimation taking into account transition probabilities
   Arlindo Oliveira

8. On The Complexity of Minimum-delay Gate Resizing Under Load-dependent Delay Model
   Rajeev Murgai

10:30-11:50 Session 6: Performance optimization

1. Complexity of performance optimization under rise and fall parameters
   Rajeev Murgai

2. Delay-constrained Area Recovery Via Layout-driven Buffer Optimization
   Rajeev Murgai

3. Performance Optimization Using A Network Flow Algorithm
   Yutaka Tamiya

11:50-1:00 Focus Groups II

1:00-2:00 LUNCH

2:00-3:20 Session 7: Satisfiability and covering

1. Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning
   Joao P Marques-Silva, Luis Guerra E Silva,

2. Incremental boolean satisfiability and its application to delay fault testing
   Joonyoung Kim

3. The Making of AURA II
   Tiziano Villa

3:20-3:40 BREAK

3:40-5:00 Session 8: On Boolean node creation

1. A Fast Algorithm for Three-Level Logic Optimization
   Elena Dubrova

2. On the Generation of Multiplexer Circuits for Pass Transistor Logic
   Christoph Scholl

3. An Efficient Method for Generating Kernels on Implicit Cube Set Representations
   Hiroshi Sawada

6:00-8:00 Banquet (Granlibakken)

Wednesday, June 30

8:30-9:50 Session 9: Logic optimization

1. Logic Optimization Using Regularity Extraction
   Thomas Kutzschebauch

2. SPFD-based Wire Removal in a Network of PLAs
   Sunil P Khatri, Subarnarekha Sinha, Andreas Kuehlmann, Robert K Brayton, Alberto Sangiovanni-Vincentelli

3. Experiments on Flexibilities for Logic and Routing Optimization in FPGAs
   Balakrishna Kumthekar

9:50-10:10 BREAK

10:10-11:30 Session 10: Performance and power optimization

1. A Robust Solution to the Timing Convergence Problem in High-Performance Design
   Narendra Shenoy

2. Gate Sizing Using a Statistical Delay Model
   Etienne Jacobs

3. Reducing Power in Pass Transistor Circuits
   Reginaldo Tavares

11:30-12:30 Focus Groups III: Wrap-up

12:30-2:00 LUNCH and planning for next IWLS