7:45-8:30 a.m.        BREAKFAST

8:30 a.m.:  Welcome from the Chairs
 

Session Chair:  Leon Stok
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8:30-9:45 a.m.    SESSION #1:  Structured Logic Synthesis
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#1.1. "Metrics for Structural Logic Synthesis"   [full talk]
           P.Kudva, A. Sullivan, W. Dougherty

#1.2. "Regular Fabrics In Deep Sub-Micron Integrated-Circuit Design"   [full talk]
           Fan Mo, Robert K. Brayton

#1.3. "Topologically Constrained Logic Synthesis"   [full talk]
           S. Sinha, A. Mishchenko, R. Brayton
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9:45-10:30 a.m.    Coffee and Poster Session #1
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P1.1. "Optical Realizations of Reversible Logic"
             Anas Al-Rabadi, Lee W. Casperson

P1.2. "Partitioning Effects on Estimated Wire
               Length for Mixed Macro  and  Standard Cell Placement"
                Theodore W. Manikas, Gerald R. Kane

P1.3. "An Approach to Designing Complex Reversible Logic Gates"
                Pawel Kerntopf

P1.4.  "On Low Power High Level Synthesis Using Genetic Algorithms"
                Mohamed A. Elgamel, Magdy A. Bayoumi

P1.5. "Layout-Aware Synthesis Methodology for Analog Systems Based
               on Combined Block Sizing, Floorplanning and Global Routing"
            Hua Tang, Alex Doboli

P1.6. "Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations"
            Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alex Petrenko,
                    Alberto L. Sangiovanni-Vincentelli

P1.7. "A Fast Heuristic Algorithm for Disjunctive
             Decomposition of Boolean Functions"
            Tomas Bengtsson, Andres Martinelli, Elena Dubrova

P1.8. "A Methodology for Core Placement and Bus Synthesis under Time,
               Area and Energy Consumption Constraints"
            Natt Thepayasuwan, Alex Doboli

P1.9. "An Efficient Two-Level Filter Scheme for Low Power Cache"
            Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan

P1.10.  "Linearity of Word-Level Circuit Models: New Understanding"
            S.N. Yanushkevich, V.P. Shmerko, V.D. Malyugin, P. Dziurzanski

P1.11.  "Improving Static Ordering of BDDs for Reachability Analysis"
            Jorgiano Vidal, David Deharbe, Dominique Borrione

P1.12. "Improving Sequential ATPG Using SAT Methods"
            Mukul R Prasad, Michael Hsiao, Jawahar Jain

P1.13. "Nonlinear Sifting of Decision Diagrams"
                Pawel Kerntopf

P1.14. "Enhanced SPFD Rewiring on Improving Rewiring Capability"
                Jason Cong, Joey (Yizhou) Lin, Wangning Long
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Session Chair:    TBA
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10:30-12:00 p.m.    SESSION #2:  Reconfigurable Architectures
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#2.1. "A Reconfigurable Architecture and Associated Synthesis Methodology
            for High Speed Packet Classification"  [full talk]
           Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz

#2.2.  "Field Modifiable Architecture and Its Design Methodology --
            System Design Without Logic Synthesis"   [full talk]
           Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto,
                   Satoshi Komatsu, Masahiro Fujita

#2.3.  "Synthesis of Morphable Multipliers"   [full talk]
                Silviu Chiricescu, Michael Schuette,  Herman Schmit, Robin Glinton

#2.4.  "Encoding of Boolean Functions and Its Application to
            LUT Cascade Synthesis"  [short talk]
           Alan Mishchenko, Tsutomu Sasao
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12:00-2:00 pm:         LUNCH and FOCUS GROUP MEETING #1

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Session Chair:  Marek Perkowski
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2:00-2:50 p.m.     SESSION #3:  Novel Design Styles
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#3.1. "Technology Mapping for Chemically Assembled Electronic Nanotechnology" [full talk]
           Petra Farm, Elena Dubrova

#3.2.  "Reversible Logic Circuit Synthesis"   [full talk]
                Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
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2:50-3:45 p.m.    Coffee and Poster Session #2
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P2.1. "ZBDD-Based Backtrack Search SAT Solver"
                Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah

P2.2. "Efficient Gate and Input Ordering for Circuit-to-BDD Conversion"
            Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah

P2.3. "Low Power Optimization Techniques for BDD
            Mapped Circuits Finite State Machines"
              Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitch Thornton

P2.4. "A Practical Approach to Cycle Bound Estimation for Property Checking"
                Chia-Chih (Jack) Yen, Kuang-Chien (KC) Chen, Jing-Yang Jou

P2.5. "Visualisation of Coding Conflicts in Asynchronous Circuit Design"
                A. Madalinski, A. Bystrov, A. Yakovlev

P2.6. "The Automatic Generation of Application Specific Processors"
                S.G. Gibb, L.E. Turner

P2.7. "A LUT based Approach for High Level Synthesis on FPGAs"
            Loic Lagadec, Bernard Pottier, Oscar Villellas,
                    Erwan Fabiani, Catherine Dezan

P2.8. "A Boolean Paradigm in Multi-Valued Logic Synthesis"
            Alan Mishchenko, Robert K. Brayton

P2.9. "Majority-Based Decomposition of Carry Logic in Binary Adders"
            Leyla Nazhandali, Karem A. Sakallah

P2.10. "Simplifying Constraint Solving in Random Simulation Generation"
            Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley

P2.11. "Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net"
                Anh Vu Dinh Duc, Laurent Fesquet, Marc Renaudin

P2.12. "Logic Synthesis of Reversible Wave Cascades"
            Alan Mishchenko, Marek Perkowski
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Session Chair:  Michel Berkelaar
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3:45-5:15 p.m.    SESSION #4:  Custom, PTL and Dynamic Circuits
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#4.1.  "Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations"   [full talk]
           Hui-Yuan Song, R. Iris Bahar, Joel Grodstein

#4.2.  "Efficient Layout Synthesis Algorithm for PassTransistor Logic Circuits"   [full talk]
           Rupesh S. Shelar, Sachin S. Sapatnekar

#4.3.  "A Constructive Matching Algorithm for Library-Based Domino
            Technology Mapping"  [full talk]
           Xinning Wang, Prashant Sawkar, Barbara Chappell

#4.4.  "Recognition of Transistor Level Complex Sequential and  Dynamic Circuits
            using  State Based BDD's"   [short talk]
           Federico Politi
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BANQUET/BOAT RIDE:    boarding 6:00-7:00 p.m., cruise/dinner 7:00-9:00 p.m.  (click here)
 

7:45-8:30 a.m.        BREAKFAST
 

Session Chair:  Robert Brayton
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8:30-10:10 a.m.    SESSION #5:  Restructuring Logic Transformations
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#5.1.  "Multi-Level Circuit Clustering for Delay Minimization"   [full talk]
           C.N. Sze, Ting-Chi Wang

#5.2.  "Bi-Decomposition and Tree-Height Reduction for Timing Optimization"   [full talk]
                Jordi Cortadella

#5.3.  "Synthesis of Asynchronous Circuits with Predictable Latency" [full talk]
           A. Bystrov, A. Yakovlev

#5.4.  "Logic Optimization for Asynchronous SI Controllers using Transduction Method"   [full talk]
           Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya
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10:10-10:55 a.m.    Coffee and Poster Session #3
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P3.1. "On-line Error Detection in a Carry-free Adder"
            Whitney J. Townsend, Mitchell A. Thornton, Parag Lala

P3.2. "Model Generation and Gate Level Abstraction of  Complex CMOS Custom
               Designs for Functional and DFT Validation"
            Amit Tandon, Federico Politi

P3.3. "Reversible Logic Synthesis by Iterative Compositions"
               Andrey Khlopotine, Marek Perkowski, Pawel Kerntopf

P3.4. "Predictability: Definition, Analysis and Optimization"
                Ankur Srivastava and Majid Sarrafzadeh

P3.5. "Symmetry as a Base for a New Decomposition of Boolean Logic"
                Anas Al-Rabadi

P3.6. "High Throughput Asynchronous Domino Using Dual Output Buffer"
                Masayuki Tsukisaka, Masashi Imai, Takashi Nanya

P3.7. "Experimental Study on Cell-Base High-Performance Datapath Design"
                Masanori Hashimoto, Yoshiteru Hayashi, Hidetoshi Onodera

P3.8. "On the Impact of Fanout Optimization and Redundant
            Buffer Removal for Mixed PTL Synthesis"
                Geun Rae Cho, Tom Chen

P3.9. "Technology Mapping for Low Leakage Power with
          Hot-Carrier Effect Consideration"
                Chang Woo Kang, Massoud Pedram

P3.10. "Accelerated Boolean Satisfiability-Based Scheduling for High-Level Synthesis"
                Seda Ogrenci Memik, Farzan Fallah
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Session Chair:  Mukul Prasad
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10:55 a.m. - 12:00 p.m.     SESSION #6:  Analysis Techniques
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#6.1.  "On the Verification of Sequential Equivalence"  [full talk]
                J.-H. Jiang, R.K. Brayton

#6.2.  "Binary Time Frame Expansion"   [short talk]
                Farzan Fallah

#6.3.  "Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions"   [full talk]
                Rene Krenz, Elena Dubrova, Andreas Kuehlmann
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12:00-2:00 pm:         LUNCH and FOCUS GROUP MEETING #2
 

Session Chair:  Tsutomu Sasao
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2:00-3:15 p.m.        SESSION #7:  Don't Cares and Logic Optimization
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#7.1.  "Don't Care Computation in Minimizing Extended Finite State Machines
            with Presburger Arithmetic"   [full talk]
           Yunjian Jiang, Robert K. Brayton

#7.2.  "Simplification of Non-Deterministic Multi-Valued Networks"   [short talk]
           Alan Mishchenko, Robert K. Brayton

#7.3.  "Reducing Multi-Valued Algebraic Operations to Binary"   [short talk]
                J.-H. Jiang, A. Mishchenko, R. Brayton

#7.4.  "Implicit Test of Regularity for Not Completely Specified Boolean Functions"   [full talk]
                Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
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-------------------------------------------------------------------
2:50-3:45 p.m.    Coffee and Poster Session #4
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P4.1. "A Method for Synthesizing Boolean Constraints"
                Jun Yuan, Kurt Shultz, John Havlicek, Ken Albin, Adnan Aziz

P4.2. "Resynthesis and Peephole Transformations for
            the Optimization of Large-Scale Asynchronous Systems"
                Tiberiu Chelcea and Steven M. Nowick

P4.3. "Comparing Transistor-Level Implementations of  4-Input Logic Functions"
                Felipe R. Schneider, Vinicius P. Correia, Renato P. Ribas, Andre I. Reis

P4.4. "Net Buffering In The Presence Of Multiple Timing Views"
                Rajeev Murgai
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Session Chair:  Karem Sakallah
-------------------------------------------------------------------
4:00-5:15 p.m.        SESSION #8:  SAT and BDD's
-------------------------------------------------------------------
#8.1.  "Overcoming Resolution-Based Lower Bounds for SAT Solvers" [full talk]
           DoRon B. Motter, Igor L. Markov

#8.2.  "Comparison of Decision Diagrams for Multiple-Output Logic Functions"   [short talk]
           T. Sasao, Y. Iguchi, M. Matsuura

#8.3.  "VisBDD -- A Web-based Visualization Framework for OBDD Algorithms"
                                                                                                            [short demo presentation]
                C. Meinel, H. Sack, V. Schillings

#8.4.  "Modular Partitioning and Dynamic Conjunction Scheduling
            in Image Computation"   [full talk]
                Christoph Meinel, Christian Stangier
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5:15-5:45 p.m.    BREAK
 

Panel Chair:   Diana Marculescu
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5:45-7:15 p.m.     PANEL SESSION:  Optical and Mixed-Technology Systems: Where Electrons Meet Laser Beams
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 "Optical Systems 101 for EDA Practitioners"

        Jaijeet Roychowdhury
        University of Minnesota

 "Giga=1/Nano:  CAD Tools and Modeling Challenges for Giga-Scale Mixed Technology Micro-Systems"

        Steven P. Levitan
        University of Pittsburgh
 

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7:30 p.m.                  DINNER:   Dominique's Restaurant
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7:45-8:30 a.m.        BREAKFAST
 

Session Chair:  Ellen Sentovich
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8:30-9:00 a.m.        SESSION #9:  High-Level Languages and Synthesis
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#9.1.  "High-Level Synthesis from the Synchronous Language Esterel" [short talk]
                Stephen A. Edwards

#9.2.  "Concurrency in System Level Design: Conflict  Between
            Simulation and Synthesis Goals"   [short talk]
                Nick Savoiu, Sandeep Shukla, Rajesh Gupta
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Session Chair:  Iris Bahar
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9:00-9:45 a.m.        SESSION #10:  Power Issues
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#10.1.  "Optimized Power-Delay Curve Generation for Standard Cell ICs"   [short talk]
                Miodrag Vujkovic, Carl Sechen

#10.2.  "Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits"   [full talk]
           Afshin Abdollahi, Farzan Fallah, Massoud Pedram
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9:45-10:15 a.m.    COFFEE BREAK
 

Benchmark Chair:  Andreas Kuehlmann
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10:15-10:30 a.m.    Discussion:  IWLS-02 Benchmarks
-------------------------------------------------------------------

Focus Group Chair:   Yuji Kukimoto
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10:30 a.m.-12:00 p.m.        Focus Groups:  Presentation and Discussion
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12:00-2:00 pm:         LUNCH and IWLS-03 PLANNING MEETING