Wednesday, June 8, 2005

Lunch

11:45 - 1:00

Sequential Synthesis

1:15 - 2:35

Do We Waste Logic on Circuit Initialization?

N. Kitchen, A. Kuehlmann

Retiming and Resynthesis: A Complexity Perspective

Jie-Hong Jiang, R. Brayton

High-Level Optimization by Combining Retiming and Shannon Decomposition

C. Soviani, O. Tardieu, S. Edwards

Layout-driven Control Re-synthesis using Re-encoding for Timing Closure

C. Y. Yeh, M. Marek-Sadowska

Poster Session

2:35-3:20

Symmetrical, Dual and Linear Functions and Their Autocorrelation Coefficients

J. Rice, R. Jansen

High Throughput and Small Size Viterbi Decoder by Hybrid CMOS - Pseudo NMOS ACS Units

A. Jahanian, K. Akbari

Sum of Non-disjoint Cubes Covering Generation for Multi-Valued Systems of base 2, for use in Muthukrishnan-Stroud Quantum Realizable Gates: An Extension of the EXOR Covering Problem

B. Yen, P. Thompson, M. Perkowski

Making a Choice Between FDDs and BDDs

J. Rice

Modeling and Synthesis of a Conventional Floating Point Fused Multiply-Add Arithmetic Unit Using CAD Tools

J. Alghazo

Multi-threaded Reachability

D. Sahoo, S. Iyer, J. Jain, D. Dill, E. A. Emerson

Separating retiming from the initial states

A. Ayupov, M. Kishinevsky, A. Marchenko

Finding Common Double-Vertex Dominators in Circuit Graphs

M. Teslenko, E. Dobrova

The Power of Large Pulse-Optimized Quantum Libraries: Every 3-qubit Reversible Function

G. Yang, X. Song, M. Perkowski, W. Hung

Functional Decomposition using Algebraic Kernel

K. Shinozuka

A New Approach to the Use of Satisfiability in False Path Detection

F. Marques, R. Ribas, S. Sapatnekar, A. Reis

Synthesis of Reversible Circuits

A. De Vos, Y. Van Rentergem

Framework for Improved Partitioning and Automatic Task Graph Extraction for State-Based Designs

L. Demoracski

Memory-based Cross-talk Canceling CODECs for On-chip Buses

C. Duan, K. Gulati, S. Khatri

Simultaneous Optimization of Delay and Number of Operations in Multiplierless Implementation of Linear Systems

A. Hosangadi, F. Fallah, R. Kastner

Construction of Planar BDDs by Using Linearization and Decomposition

I. Levin, R. Stankovic, M. Karpovsky, J. Astola

Robust Synthesis of Asynchronous Burst-Mode Machines

G. Gill, M. Singh

Logic Synthesis

3:20 - 5:00pm

Synthesis Methodology for Built-In At-Speed Testing

Y. Li, A. Kondratyev, R. Brayton

Don't-care Computation using k-clause Approximation

K. McMillan

Simulation and Satisfiability in Logic Synthesis

J. Zhang, S. Sinha, A. Mishchenko, R. Brayton, M. Chrzanowska-Jeske

How Hard is Two-Level Logic Minimization: an Addendum to Garey&Johnson

C. Umans, T. Villa, A. Sangiovanni-Vincentelli

Integrating Logic Synthesis, Technology Mapping, and Retiming

A. Mishchenko, S. Chatterjee, J.H. Jiang, R. Brayton

Power, Reliabiltiy and Fault Tolerance

5:15 - 6:15pm

A Code Placement Technique for Improving the Performance of Processors with Defective Caches

T. Ishihara, F. Fallah

Kauffman Networks: From Nature to Electronics

E. Dubrova

Techniques for Fault Reduction in Out-of-Order Microprocessors

B. Gojman, V. Stojanovic, R. I. Bahar, R. Weiss

Dinner

6:30 - 8:00pm

Thursday, June 9, 2005

Breakfast

7:30 - 8:30am

Novel Applications of Decision Diagrams

8:30-9:50

Efficient Synthesis of Quantum Logic Circuits by Rotation-based Quantum Operators and Unitary Functional Bi-decomposition

A. Abdollahi, M. Pedram

Circuit Reliability using Symbolic Techniques

N. Miskov-Zivanov, D. Marculescu

An Efficient Graph Based Representation of Circuits and Calculation of Their Coefficients in Finite Field

A. Jabir

A new algorithm for Partitioned Model Checking

S. Iyer, E. A. Emerson, D. Sahoo, J. Jain

Poster Session

9:50 - 10:35am

Galois Switching Theory: A Uniform Framework For Multi-Level Verification

D. Pradhan, A. K. Singh, T. Rajaprabhu, A. Jabir

Efficient Post-Layout Power-Delay Curve Generation

M. Vujkovic, D. Wadkins, C. Sechen

Analytical Modeling and Reduction of Direct Tunneling Current during Behavioral Synthesis of Nanometer CMOS Circuits

S. Mohanty, V. Mukherjee, R. Velagapudi

Using exhaustive search for the discovery of new families of optimum universal permutative binary quantum gates

M. Lukac, M. Perkowski

An Improved Approach for Alternative Wires Identification

Y. C. Chen, C. Y. Wang

Exact lower bound for the number of switches in series to implement a combinational logic cell

F. Schneider, R. Ribas, S. Sapatnekar, A. Reis

Predictive Reachability Using a Sample-based Approach

D. Sahoo, S. Iyer, J. Jain, D. Dill, E. A. Emerson

Optimization Protocol based on Low Power Metrics

V. Alexandre, L. Alexis, P. Maurine, N. Azemard

GUIDO: Hybrid Verification through Distance-Guided Simulation

S. Shyam, V. Bertacco

Probabilistic Dual-Vth Leakage Optimization Under Variability: Using Stochastic Pruning

A. Davoodi, A. Srivastava

Boolean Manipulation with Decomposed Functions

S. Plaza, V. Bertacco

A General Framework for Accurate Statistical Timing Analysis Considering Correlations

V. Khandelwal, A. Srivastava

Challenges in Synthesizing Fast Control-Dominated Circuits

C. Soviani, S. Edwards

On the Exact Minimization of Path-Related Objective Functions for BDDs

R. Ebendt, R. Drechsler

A Scheduilng Method for Asynchronous Bundled-Data Implementations

R. Saito, N. Jindapetch, T. Yoneda, C. Myers

An Efficient Jitter- and Skew-aware Methodology for Clock Tree Synthesis and Analysis

R. Murgai, W. Walker, V. Wason

Equivalence Checking for Transformations and Optimizations in C Programs on Dependence Graphs

T. Matsumoto, H. Saito, M. Fujita

Invited Speakers

10:35 - 12:35

Patrick Schaumont

UCLA

Anand Rahunathan

NEC Labs, Princeton, NJ

Lunch

12:35pm - 1:35pm

Hiking trip near Lake Arrowhead

2:00 - 6:00pm

Dinner

6:30 - 8:00pm

Friday, June 10, 2005

Breakfast

7:30 - 8:30am

Technology Mapping

8:30 - 9:50am

Constructive Logic and Layout Synthesis Does Not Work

Y. Oh, E. Ernst, K. Sakallah, I. Markov

Reducing Structural Bias in Technology Mapping

S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, T. Ka

Multi-Objective Optimization during Technology Mapping

A. Mishchenko, S. Chatterjee, R. Brayton, M. Ciesielski

Building a Better Boolean Matcher

D. Chai, A. Kuehlmann

Poster Session

9:50 - 10:35am

For first 17 presentations (through Thursday morning)

Reconfigurable Logic

10:35 - 11:55

FPGA Architecture Evaluation and Technology Mapping using Boolean Satisfiability

A. Ling, D. Singh, V. Manohararajah, S. Brown

Data Partitioning for Reconfigurable Architectures with Distributed Block RAM

W. Gong, R. Kastner

Timing Driven Functional Decomposition for FPGAs

V. Manohararajah

Factorizing Multiplexers in the Datapath to Reduce Cost in FPGAs

D. Nancekievill, P. Matzgen

Lunch

12:00 - 1:00pm

Issues in High-Level Synthesis

1:15pm - 2:35pm

Physically Aware Data Communication Optimization for Hardware Synthesis

R. Kastner, W. Gong, A. Kaplan, P. Brisk, X. Hao, F. Brewer

HLS Support for Unconstrained Memory Accesses

G. Venkataramani, T. Chelcea, S. Goldstein

Polynomial-Time Graph Coloring Register Allocation

P. Brisk, F. Dabiri, J. Macbeth, M. Sarrafzadeh

Analysis and Synthesis of Weighted-Sum Functions

T. Sasao

Poster Session

2:35 - 3:15pm

For last 17 presentations (all Friday presentations)

Physical Design and Timing Analysis

3:15 - 4:55

Selective Application of Synthesis Transforms for Improved Computational Efficiency

R. Hentschke, J. Narasimhan, D. Kung

Post-Placement Rewiring by Exhaustive Search for Functional Symmetries

K-H. Chang, I. Markov, V. Bertacco

Robust Optimization using Incremental Parameterized Statistical Timing Analysis

M. Guthaus, N. Venkateswaran, V. Zolotov, C. Visweswariah

Computing Clock Skew Schedules Under Normal Process Variation

A. Hurst, R. Brayton

Variability Driven Buffer Insertion Considering Correlations

A. Davoodi, A. Srivastava