| Friday, July 31 |
| 12:30 - 1:30 : Lunch |
| 1:30 - 2:30 : Session 1 (Chair: Sunil Khatri) |
|
A Power Optimization Toolbox for Logic Synthesis and Mapping (20 min.)
Stephen Jang, Kevin Chung, Alan Mishchenko, and Robert Brayton |
|
Fault-Tolerant Synthesis using Non-Uniform Redundancy (20 min.)
Keven Woo and Matthew Guthaus |
|
DeltaSyn: An Efficient Logic Difference Optimizer for ECO Synthesis (20 min.)
Smita Krishnaswamy, Haoxing Ren, Nilesh Modi, and Ruchir Puri |
| 2:45 - 3:45 : Session 2 (Chair: Satrajit Chatterjee) |
|
The Synthesis of Cyclic Dependencies with Craig Interpolation (20 min.)
John Backes and Marc Riedel |
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Tree Decomposition Using k-Input Cuts (20 min.)
Donald Chai and Andreas Kuehlmann |
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Incremental Sequential Equivalence Checking and Subgraph Isomorphism (20 min.)
Sayak Ray, Alan Mishchenko, and Robert Brayton |
| 3:45 - 4:45 : Poster Session 1 |
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Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost
Robert Wille, Mehdi Saeedi, and Rolf Drechsler |
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Achieving High-Quality Verification at Early Design Phases via Native Symbolic Methodologies
Hong-Zu Chou, Kai-Hui Chang, and Sy-Yen Kuo |
|
On the Number of LUTs to Realize Sparse Logic Functions
Tsutomu Sasao |
|
A Variation-Tolerant Scheduler for Better Than Worst-Case Behavioral Synthesis
Jason Cong, Albert Liu, and Bin Liu |
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Variability Tolerance on Throughput and Power for 3D Chip-Multiprocessors
Iris Hui-Ru Jiang and Wan-Yu Lee |
|
Temperature-Aware Dual-Vt Assignment for Leakage Minimization
Junjun Gu, Lin Yuan, and Gang Qu |
|
Testing in Context and Synthesis of the Unknown Component:Two Faces of the Same Coin
Alex Petrenko, Nina Yevtushenko, and Tiziano Villa |
|
1-of-N Domino Logic Synthesis
Craig Files |
| 6:00 - 7:30 : Dinner and Invited Talk I (Chair: Igor Markov) |
|
Embedded Security in the Automotive World: Feature Activation, Software Integrity and Secure Vehicle-to-Vehicle Communication
Kai Schramm and Andre Weimerskirch |
| Saturday, Aug. 1 |
| 8:00 - 9:00 : Breakfast |
| 9:00 - 10:00 : Session 3 (Chair: Smita Krishnaswamy) |
|
A Decomposition Algorithm to Structure Arithmetic Circuits (20 min.)
Ajay Verma, Philip Brisk, and Paolo Ienne |
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Bit-Level Transformation and Optimization for Hardware Synthesis of Algorithmic Descriptions (20 min.)
Jiyu Zhang, Zhiru Zhang, Jason Cong, Sheng Zhou, Mingxing Tan, Xianhua Liu, and Xu Cheng |
|
Global Interconnect Reduction By Data Transfer Through Functional Units (20 min.)
Taemin Kim and Xun Liu |
| 10:15 - 11:30 : Session 4 (Chair: Valeria Bertacco) |
|
Synthesizing Sequential Register-Based Computation with Biochemistry (20 min.)
Adam Shea, Brian Fett, Marc Riedel, and Keshab Parhi |
|
An Algorithm for Identifying Dominant-Edge Metabolic Pathways (20 min.)
Ehsan Ullah, Kyongbum Lee, and Soha Hassoun |
|
Spinto: A High-performance Solver for Energy Minimization in Ising Spin-glasses (20 min.)
Hector Garcia and Igor Markov |
|
Compacting Test Vector Sets via Strategic Use of Implications (15 min.)
Iris Bahar, Kundan Nepal, Jennifer Dworak, and Nuno Alves |
| 11:30 - 12:30 : Poster Session 2 |
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Reliable Circuit Design using Linear Programming Based on Probabilistic Gate Model
Xin He and Afshin Abdollahi |
|
KL-Cuts
Osvaldo Martinello Junior, Felipe Marques, Renato Ribas, and Andre Reis |
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A Runtime Power-Reduction Technique Using Adaptive Forward Body Bias
Syed Kadry and Afshin Abdollahi |
|
A Library-Based Synthesis Approach for Reversible Logic
Mehdi Saeedi, Mehdi Sedighi, and Morteza Saheb Zamani |
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1-of-N Domino Logic In Place Optimization
Craig Files |
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Ways to Improve Heuristic Algorithms for Reversible Circuit Synthesis
Marek Szyprowski and Pawel Kerntopf |
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The Observed Role of Structure in Logic Synthesis Examples
Petr Fiser and Jan Schmidt |
|
Automatic Microarchitectural Pipelining
Marc Galceran-Oms, Jordi Cortadella, Michael Kishinevsky, and Dmitry Bufistov |
|
Multi-Operand Adder Synthesis on FPGAs using Generalized Parallel Counters
Taeko Matsunaga, Shinji Kimura, and Yusuke Matsunaga |
| 12:30 - 1:30 : Lunch |
| 1:30 - 3:00 : Session 5 (Chair: Iris Bahar) |
|
A Heuristic Approach to Bottleneck Removal in Asynchronous Pipelined Systems (20 min.)
Gennette Gill and Montek Singh |
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Asynchronous networks with positive and negative thresholding (15 min.)
Yu Zhou and Alex Yakovlev |
|
Reducing Reversible Circuit Cost by Adding Lines (20 min.)
D. Michael Miller, Robert Wille, and Rolf Drechsler |
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Alleviating the Voltage Scaling Limitations of Razor-based Designs (15 min.)
John Sartori and Rakesh Kumar |
|
A Formal Methodology for Verifying Domino Logic Circuits with Sneak Paths (20 min.)
Adrian Isles, Edmond Bures, Craig Files, Mark Nodine, and Laura Potter |
| 3:00 - 4:30 : Visit of Campanile and UC Berkelely Museum of Anthropology |
| 4:30 - 6:00 : Tour of Berkeley Campus |
| 6:30 - 8:00 : Dinner and Invited Talk II (Chair: Igor Markov) |
|
Imperfection-Immune Digital VLSI using Carbon Nanotube Field Effect Transistors
Subhasish Mitra |
| Sunday, Aug. 2 |
| 8:00 - 9:00 : Breakfast |
| 9:00 - 10:00 : Session 6 (Chair: Soha Hassoun) |
|
Minimal Logic Duplication for Post-Retiming Reset Equivalence (20 min.)
Aaron Hurst |
|
SSRR: Peak Current Reduction by Simultaneous State Replication and Re-Encoding (20 min.)
Junjun Gu, Lin Yuan, and Gang Qu |
|
On Preserving Signal Integrity in Technology Mapping (20 min.)
Fang-Yu Fan, Hung-Ming Chen, and I-Min Liu |
| 10:15 - 11:15 : Session 7 (Chair: Iris Bahar) |
|
The Synthesis of Combinational Logic to Generate Probabilities (20 min.)
Weikang Qian, Marc Riedel, Kia Bazargan, and David Lilja |
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Interpolating Functions from Large Boolean Relations (20 min.)
Jie-Hong Jiang, Hsuan-Po Lin, and Wei-Lun Hung |
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Fast Boolean Factoring with Multi-Objective Goals (20 min.)
Andre Reis, Anders Rasmussen, Leomar da Rosa Junior, and Renato Ribas |
| 11:30 - 12:45 : Session 8 (Chair: Alan Mishchenko) |
|
LUTMIN: FPGA Logic Synthesis with MUX-based and Cascade Realizations (20 min.)
Tsutomu Sasao and Alan Mishchenko |
|
IPR: InPlace Reconfiguration for FPGA Fault Tolerance (20 min.)
Zhe Feng, Yu Hu, Lei He, and Rupak Majumdar |
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Layout-Driven FPGA Retiming for Mitigation of Variational Single-Event Transient Faults (20 min.)
Wenyao Xu, Jia Wang, Yu Hu, and Lei He |
|
A Power-aware Post-processing under depth constraint for LUT-based FPGA technology mapping (15 min.)
Taiga Takata and Yusuke Matsunaga |
| 12:45 - 2:00 : Lunch |