IWLS 2011 will be held in Room 1202 at the University of California - San Diego, Computer Science and Engineering Department, Building EBU3B.
| Friday June 3, 2011 |
| Noon - 1:30pm : Lunch |
| 1:30pm - 1.40pm: Chairs' Welcome |
| 1:40 - 2:55 : Session 1 -
Algorithms and Methodologies for Logic Synthesis Session Chair: Valeria Bertacco |
|
Synthesis of GPC-based Compressor Trees Targeting Delay and Power Aware Implementation on FPGAs
Taeko Matsunaga, Shinji Kimura Waseda U. and Yusuke Matsunaga Kyushu U. |
|
Synthesis of Parallel Binary Machines
Elena Dubrova, KTU Sweden |
|
Logical-Depth-Oriented Reversible Logic Synthesis
Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi and Mehdi Saeedi, Amirkabir |
| 3.15 - 4:40 : Session 2 - Validation, Debug and Test Session Chair: Alan Mishchenko |
|
Improving At-speed Testability at Early Design Stages
Kai-hui Chang, Hong-Zu Chou Avery Design Systems, and Igor L. Markov U. Michigan |
|
Formally Enhanced Verification at Runtime to Ensure NoC Functional Correctness
Ritesh Parikh, Rawan Abdel-Khalek and Valeria Bertacco, U. Michigan |
|
Simulation-based Signal Selection for State Restoration in Silicon Debug
Debapriya Chatterjee and Valeria Bertacco, U. Michigan |
| 4:50 - 5:25 : Poster Session Session Chair: Ali Irturk |
|
Post-Mapping Optimization based on Boolean Satisfiability
Tobias Welp UC Berkeley, Andreas Kuehlman Coverity, and Smita Krishnaswamy Columbia U. |
|
Extensions of Cartesian Genetic Programming for Optimization of Combinational Circuits
Zdenek Vasicek and Lukas Sekanina, Brno UT |
|
An Improved Sum Computation Block for adders with High Sparseness
Chetan Vudadha, Sai Phaneendra, Syed Ershad Ahmed, Sreehar Veeramachaneni, Moorthy Muthukrishnan and Srinivas M.B., BITS Pilani |
|
Symmetry in Reversible Functions and Circuits
Pawel Kerntopf and Marek Szyprowski, Warsaw UT |
| 5.30 - 6.30 : Invited Talk I Moderator: Ilya Wagner |
|
Post-Silicon Validation and Debug Rand Gray, Intel |
| 7.30 - 9.30 : Dinner |
| Saturday June 4, 2011 |
| 8:00 - 8.30 : Breakfast |
| 8:30 - 9:45 : Session 3 - Logic Optimization by Balancing, Rewriting & Rewiring Session Chair: Marc Riedel |
|
Delay Optimization Using SOP Balancing
Alan Mishchenko, Robert K. Brayton UC Berkeley, Stephen Jang LogicMill, Victor Kravets IBM |
|
AIG Rewriting Using 5-Input Cuts
Nan Li and Elena Dubrova, KTH Sweden |
|
A Rewiring Algorithm for Threshold Logic Circuits Pin-Yi Kuo, Chun Yao Wang and Ching-Yi Huang, NTHU |
| 9.55 - 11.10 : Session 4 - Design and Analysis for Reliability
Session Chair: Elena Dubrova |
|
Cardio: Adaptive CMPs for Reliability through Dynamic Introspective Operation
Andrea Pellegrini and Valeria Bertacco, U. Michigan |
|
A Robust CODC-based Heuristic to Extract Observability Don't Care Set
Taiga Takata and Yusuke Matsunaga, Kyushu U. |
|
Proving Stabilization Using Liveness to Safety Conversion
Sayak Ray and Robert Brayton, UC Berkeley |
| 11.20 - 12.20 : Invited Talk II Moderator: Ryan Kastner |
|
Security through Synthesis: Towards Trustworthiness as a Hardware Design Constraint (Rather than an Afterthought) Tim Sherwood, UC Santa Barbara |
| 12:20 - 1:25 : Lunch |
| 1.25 - 2.25: Special Session - Novel Applications of Reconfigurable Logic Circuits
Chair: Andrea Pellegrini |
|
CoRAM: An FPGA Architecture for Computing James Hoe, CMU |
|
Using Reconfigurable Logic to Simulate Computer Systems Derek Chiou, UT Austin |
|
Compound circuits in multi-accelerator architectures: how to balance between flexibility & specialization Sami Yehia Thales |
| 2.35 - 3.50 : Session 5 - Functional and Physical Optimization Session Chair: Igor Markov |
|
Applying Verification Intent for Design Customizat'n via Property Mining under Constrained Testbenches
Chih-Neng Chung NTU, Chia-Wei Chang NCUT, Kai-Hui Chang Avery Design Systems, Sy-Yen Kuo, NTU |
|
Routing Wire Optimization through Generic Synthesis on FPGA Carry Chains
Hadi Parandeh-Afshar EPFL, Grace Zgheib Lebanese American University, Philip Brisk UC Riverside, Paolo Ienne EPFL |
|
How Much Randomness Makes a Tool Randomized?
Petr Fiser, Jan Schmidt, CTU Prague |
| 4.00 - 5.00 : Invited Talk III Moderator: Philip Brisk |
|
A Response to Technological Change: Incorporating Semantics into Software Translation Scott Baden, UCSD |
| 5.00 - 10.30 : Social Event - Dinner Cruise
(Boarding at 6:30.) |
| Sunday June 5, 2011 |
| 8:45 - 9:15 : Breakfast |
| 9:15 - 10:30 : Session 6 - Data Structures and Representations for Logic Synthesis Session Chair: Philip Brisk |
|
Linear Decomposition of Logic Functions: Theory and Applications
Tsutomo Sasao, Kyushu IT |
|
Resolution Proofs as a Data Structure For Logic Synthesis
John Backes and Marc D. Riedel, U. Minnesota |
|
An Improved Encoding Technique for Gate Level Information Flow Tracking
Wei Hu NPU China, Jason Oberg UC San Diego, Ali U Irturk UC San Diego, Mohit Tiwari UC Santa Barbara, Tim Sherwood UC Santa Barbara , Dejun Mu NPU China, Ryan Kastner UC San Diego |
| 10.50 - 12:05 : Session 7 - Faster Verification Session Chair: Ilya Wagner |
|
Efficient Implementation of Property-Directed Reachability
Niklas Een, Alan Mishchenko and Robert Brayton, UC Berkeley |
|
The Benefits of Concurrency in Model Checking
Baruch Sterin, Niklas Een, Alan Mishchenko and Robert Brayton, UC Berkeley |
|
Improving Design Verifiability by Early RTL Coverability Analysis
Kai-Hui Chang Avery Design Systems, Chia-Wei Chang NCUT, Jie-Hong R. Jiang NTU, Chien-Nan Liu NCUT |
| 12.05 - 12.10 : Workshop Adjourns |
| 12.10 - 1.30 : Lunch |