IWLS 2012 will be held in 430-8 Soda Hall - Wozniak Lounge at the University of California - Berkeley, Electrical Engineering & Computer Sciences .

Friday June 1, 2012

12:00pm - 1:45pm : Lunch

1:45pm - 2:00pm: Conference Opening Philip Brisk and Ilya Wagner

2:00 - 3:30 : Session 1 - Logic Synthesis and Optimization I Session Chair: TBD

LMS: A New Logic Synthesis Method Based on Pre-Computed Library Wenlong Yang Fudan University, China Lingli Wang Fudan University, China and Alan Mishchenko UC Berkeley, USA

Functional Composition Paradigm and Applications Mayler Martins UFRGS, Brazil, Vinicius Callegaro UFRGS, Brazil, Lucas Machado UFRGS, Brazil, Renato Ribas UFRGS, Brazil and Andre Reis UFRGS, Brazil

Generalized Templates for Reversible Logic and Their Uses Pawel Kerntopf Warsaw University of Technology and University of Lodz, Poland and Marek Szyprowski Warsaw University of Technology, Poland

4:00pm - 5:30pm : Session 2 - Satisfiability and Verification Session Chair: TBD

Program Verification Using Property Directed Reachability Tobias Welp UC Berkeley, USA and Andreas Kuehlmann Coverity Inc., USA

Efficient Transformation of Various Timed Characteristic Functions for Satisfiability Solving Yi-Ting Chung National Taiwan University, Taiwan and Jie-Hong Roland Jiang National Taiwan University, Taiwan

Variable Time-Frame Abstraction Alan Mishchenko UC Berkeley, USA, Niklas Een UC Berkeley, USA, Robert Brayton UC Berkeley, USA, Jason Baumgartner IBM, USA, Hari Mony IBM, USA and Pradeep Nalla IBM, India

5:45pm - 6:45pm : Keynote Moderator: TBD

Exascale visualization: get ready for a new world Dr. Hank Childs, Computer Systems Engineer, Visualization Group, Computational Research Division, Lawrence Berkeley National Laboratory Professional Researcher, Department of Computer Science, University of California, Davis

7:30pm - 10:00pm : Dinner

Saturday June 2, 2012

8:00am - 9.00am : Breakfast

9:00am - 10:30am : Session 3 - Networks and Protocols Session Chair: TBD

A TCAM Simplification for Packet Classification Infall Syafalni Kyushu Institute of Technology, Japan and Tsutomu Sasao Kyushu Institute of Technology, Japan

LinkMiser: Resource Conscious Routing and Reconfiguration in Faulty On-Chip Networks Ritesh Parikh University of Michigan and Valeria Bertacco University of Michigan

Protocol converter synthesis by solving language equations Giovanni Castagnetti University of Verona, Italy, Matteo Piccolo University of Verona, Italy, Tiziano Villa University of Verona, Italy, Nina Yevtushenko Tomsk State University, Russia, Robert Brayton UC Berkeley, USA and Alan Mishchenko UC Berkeley, USA

10:30am - 11:10am : Coffee Break and Poster Session Session Chair: TBD

Logic Synthesis for Disjunctions of Boolean Functions Baruch Sterin UC Berkeley, USA, Alan Mishchenko UC Berkeley, USA, Niklas Een UC Berkeley, USA and Robert K. Brayton UC Berkeley, USA

K-cuts and KL-cuts on Netlist Representations for Local Remapping Lucas Machado UFRGS, Brazil, Renato Ribas UFRGS, Brazil and Andre Reis UFRGS, Brazil

LUT Structure for Delay: Cluster or Cascade? Alan Mishchenko UC Berkeley, USA

An Analysis of Using Synthesis of Transistor Networks in 65nm Gerson Scartezzini UFRGS, Brazil and Ricardo Reis UFRGS, Brazil

11:15am - 12:00pm : Keynote Moderator: TBD

Transforming Biology to an Information Science Dr. Ajay Royyuru, Senior Manager, Computational Biology Center Thomas J. Watson Research Center, Yorktown Heights, NY USA

12:00pm - 1:45pm : Lunch

1:45pm - 3:15pm: Special Session - Software Verification and Testing Chair: Debapriya Chatterjee

Corral: A Solver for Reachability-Modulo-Theories Shaz Qadeer Microsoft Research, USA

Automated Atomicity-Violation Fixing Ben Liblit University of Wisconsin-Madison, USA

Debugging Concurrent Programs Vineet Kahlon NEC Laboratories America, USA

3.45pm - 5.45pm : Session 4 - Decision Diagrams and Sequential AIGs Session Chair: TBD

Who Watches the Watchers: Toward Provably-correct Decision Diagram Code Invited Paper Yousra Lembachar UC Riverside, USA, Ryan Rusich UC Riverside, USA, Iulian Neamtiu UC Riverside, USA, Gianfranco Ciardo UC Riverside, USA

New Results on BDD Sizes and Implications for Verification Rick McGeer Hewlett Packard, USA

A Semi-Canonical Form for Sequential AIGs Alan Mishchenko UC Berkeley, USA, Niklas Een UC Berkeley, USA, Robert Brayton UC Berkeley, USA, Michael Case Calypto Design Systems, USA, Pankaj Chauhan Calypto Design Systems, USA and Nikhil Sharma Calypto Design Systems, USA

Manipulating Time-Series Datasets with Binary Decision Diagrams Stergios Stergiou Fujitsu Labs of America, USA and Jawahar Jain Fujitsu Labs of America, USA

6:00pm - 7:00pm : Keynote Moderator: TBD

TBD Prof. Eamonn Keogh, Professor, UC Riverside

7.30pm - 10.00pm : Dinner and Social Event

Sunday June 3, 2012

8:00am - 9:00am : Breakfast

9:00am - 10:30am : Session 5 - Sequential Equivalence Checking and Fault Simulation Session Chair: TBD

Sequential Equivalence Checking for Clock-Gated Circuits Robert Brayton UC Berkeley, USA, Hamid Savoj Savoj Solutions, USA, Alan Mishchenko UC Berkeley, USA and David Berthelot Coder Charts, USA

Using Speculation for Sequential Equivalence Checking Robert Brayton UC Berkeley, Niklas Een UC Berkeley and Alan Mishchenko UC Berkeley

An Efficient Fault Simulation Algorithm for Analyzing Incorrect State Transitions Induced by Soft Errors in Sequential Circuits Taiga Takata Kyushu University, Japan, Masayoshi Yoshimura Kyushu University, Japan and Yusuke Matsunaga Kyushu University, Japan

10.45am - 12:15pm : Session 6 - Logic Synthesis and Optimization II Session Chair: TBD

The Synthesis of Complex Arithmetic Computation on Stochastic Bit Streams Using Sequential Logic Peng Li University of Minnesota, USA, Weikang Qian University of Michigan-Shanghai Jiao Tong University Joint Institute, China, David Lilja University of Minnesota, USA, Marc Riedel University of Minnesota, USA and Kia Bazargan University of Minnesota, USA

A Tight Consistent Delay Model for Black Boxes Robert Brayton UC Berkeley, USA, Niklas Een UC Berkeley, USA and Alan Mishchenko UC Berkeley, USA

Read Polarity Once Functions Vinicius Callegaro UFRGS, Brazil, Mayler Martins UFRGS, Brazil, Renato Ribas UFRGS, Brazil, and Andre Reis UFRGS, Brazil

12:45pm - 1:00pm : Lunch

1:00pm - 2:30pm : Session 7 - Reliability and Test Session Chair: TBD

Well-foundedness in Credit-Based Flow-Control Systems Sayak Ray UC Berkeley, USA and Robert Brayton UC Berkeley, USA

Generating Local Test Point Activation Signals Using Controllability Don't-Cares Kai-Hui Chang Avery Design Systems, USA, Chia-Wei Chang National Central University, Taiwan, Jie-Hong Roland Jiang National Taiwan University, Taiwan and Chien-Nan Liu National Taiwan University, Taiwan

How Can We Build More Reliable EDA Software? David E. Wallace Blue Pearl Software, USA and Scott Aron Bloom Blue Pearl Software, USA

2:30pm - 2:40pm : Closing Remarks