 2018 Co-located with the Design Automation Conference 
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27th International Workshop on Logic & Synthesis June 23 – 24, 2018 Moscone Center West — San Francisco, CA
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Our sponsors
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| IWLS 2018 Technical Program |
| Saturday June 23, 2018 |
| 8:50am - 9:00am: Workshop Opening |
| 9:00am - 10:00am: Keynote 1: The Circuit Complexity Project at NIST Rene Peralta, NIST, USA Session Chair: Pierre-Emmanuel Gaillardon |
| 10:00am - 10:30am: Coffee Break |
| 10:30am - 12:00am: Session 1: Synthesis Packages and Toolkits Session Chair: Luca Amaru |
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Integrating an AIG Package, Simulator, and SAT Solver
Alan Mishchenko and Robert Brayton (UC Berkeley, USA) |
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The EPFL Logic Synthesis Libraries
Mathias Soeken, Heinz Riener, Winston Haaswijk and Giovanni De Micheli (EPFL, Switzerland) |
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Parallel AIG Rewriting
Vinicius Neves Possani (UFRGS, Brazili), Yi-Shan Lu (UT Austin, USA), Alan Mishchenko (UC Berkeley, USA), Keshav Pingali (UT Austin, USA), Renato Perez Ribas and Andre Inacio Reis (UFRGS, Brazil) |
| 12:00am - 2:00pm: Lunch Break |
| 2:00pm - 3:30pm: Session 2: Quantum Logic, Reversible Logic, and Multi-Level Logic Session Chair: Dirk Stroobandt |
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Estimating Single-Target Gate T-count using Spectral Classification
Giulia Meuli, Mathias Soeken (EPFL, Switzerland), Martin Roetteler (Microsoft Research, USA), D. Michael Miller (University of Victoria, Canada), Matthew Amy (University of Waterloo, Canada), Nathan Wiebe (Microsoft Research, USA) and Giovanni De Micheli (EPFL, Switzerland) |
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Reversible Logic Synthesis for Incompletely Specified Functions
He-Teng Zhang and Jie-Hong Roland Jiang (National Taiwan University, Taiwan) |
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Exact Multi-Level Logic Benchmark Generation
Walter Lau Neto (UFRGS, Brazil), Felipe Dos Santos Marranghello (KTH, Sweden), Vinicius Neves Possani, André Inácio Reis and Renato Perez Ribas (UFRGS, Brazil) |
| 3:30pm - 4:00pm: Coffee Break |
| 4:00pm - 5:30pm: Session 3: Arithmetic and Logic Session Chair: Alan Mishchenko |
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Logic Synthesis for Multiple-Output Linear Circuits
Tsutomu Sasao (Meiji University, Japan) |
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A Canonicalization Procedure of Threshold Logic Functions and Its Applications
Siang-Yun Lee, Nian-Ze Lee and Jie-Hong Roland Jiang (National Taiwan University, Taiwan) |
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Craig Interpolants in Finite Fields using Algebraic Geometry: Theory and Application
Utkarsh Gupta (University of Utah, USA), Irina Ilioaea (Georgia State University, USA), Priyank Kalla (University of Utah, USA), Florian Enescu (Georgia State University, USA), Vikas Rao and Arpitha Srinath (University of Utah, USA) |
| 5:30pm - 6:00pm: IWLS 2018 Programming Contest: All the Best!
Session Chair: Mathias Soeken |
| Sunday June 24, 2018 |
| 8:30am - 9:30am: Keynote 2: Looking Outside CMOS
Antun Domic, Synopsys Inc., USA Session Chair: Giovanni De Micheli |
| 9:30am - 10:30am: Session 4: Decomposition and Rewriting Session Chair: Vinicius Callegaro |
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Support-Reducing Functional Decomposition for FPGA Technology Mapping
Lucas Machado and Jordi Cortadella (Universitat Politecnica de Catalunya, Spain) |
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Structural Rewriting in XOR-Majority Graph
Zhufei Chu (Ningbo University, China), Mathias Soeken (EPFL, Switzerland), Yinshui Xiai and Lunyao Wang (Ningbo University, China) |
| 10:30am - 11:00am: Coffee Break |
| 11:00am - 12:00pm: Session 5: Verification and Security Session Chair: Mayur Bubna |
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Coverage-Guided CTL Property Enumeration for Understanding Models of Reactive Systems
Gianluca Martino (TUHH, Germany), Heinz Riener (EPFL, Switzerland) and Goerschwin Fey (TUHH, Germany) |
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SWAN: Hardware Trojan Security With Ambiguous Netlists
Timothy Linscott, Valeria Bertacco, Todd Austin and Opeoluwa Matthews (University of Michigan, USA) |
| 12:00am - 2:00pm: Lunch Break |
| 2:00pm - 3:00pm: Keynote 3: MemComputing with Self-Organizing Logic Gates Massimiliano Di Ventra, UCSD, USA Session Chair: Jie-Hong Roland Jiang |
| 3:00pm - 4:00pm: Coffee Break + Poster Session |
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Patch Function Input Selection Methods for Efficient Multi-Target Rectification
Yusuke Kimura, Amir Masoud Gharehbaghi and Masahiro Fujita (University of Tokyo, Japan) |
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Resolving Unknown Components in Arithmetic Circuits using Computer Algebra Methods
Vikas Rao, Utkarsh Gupta (University of Utah, USA), Irina-Georgeana Ilioaea (Georgia State University, USA), Priyank Kalla (University of Utah, USA) and Florian Enescu (Georgia State University, USA) |
| 4:00pm - 5:30pm: Session 6: Random or Not Random Session Chair: Masahiro Fujita |
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Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM
Infall Syafalni (Logic Research Co., Japan), Tsutomu Sasao (Meiji University, Japan) and Xiaoqing Wen (Kyushu Institute of Technology, Japan) |
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Using Resolution Splitting to Enhance Performance of Deterministic Bit-Stream Computing
M. Hassan Najafi, Sayed Abdolrasoul Faraji, Bingzhe Li, David Lilja and Kia Bazargan (University of Minnesota, USA) |
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Fast-Converging, Scalable, Deterministic Bit-Stream Computing using Low-Discrepancy Sequences
M. Hassan Najafi, David Lilja and Marc Riedel (University of Minnesota, USA) |
| 5:30pm - 5:50pm: Closing Remarks |